traffic light verilog
module fsm( input clk,rst, output reg red1,green1,yellow1,red2,green2,yellow2,red3,green3,yellow3,red4,green4,yellow4 ); reg [1:0]state,next_state; parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11; always@(posedge clk,posedge rst) begin if(rst) state<=s0; else state<=next_state; end always@(state) begin case(state) s0:next_state<=s1; s1:next_state<=s2; s2:next_state<=s3; s3:next_state<=s1; endcase end always@(state) begin case(state) s0:{red1,green1,yellow1,red2,green2,yellow2,red3,green3,yellow3,red4,green4,yellow4}<=12'b100100010001; s1:{red1,green1,yellow1,r...